Sharp: Efficient Loop Scheduling with Data Hazard Reduction on Multiple Pipeline Dsp Systems1

Computation intensive DSP applications usually require parallel/pipelined processor in order to achieve specific timing requirements. Data hazards are a major obstacle against the high performance of pipelined systems. This paper presents a novel efficient loop scheduling algorithm that reduces data hazards for those DSP applications. Such an algorithm has been embedded in a tool, called SHARP, which schedules a pipelined data flow graph to multiple pipelined units, while hiding the underlying data hazards and minimizing the execution time. This paper reports significant improvement for some well-known benchmarks, showing the efficiency of the scheduling algorithm and the flexibility of the simulation tool. INTRODUCTION In order to speedup current high performance DSP systems, multiple pipelining is one of the most important strategies that should be explored. Nonetheless, it is wellknown that one of the major problems on applying the pipelining technique is the delay caused by dependencies between instructions, called hazards. Hazards prevent the next instruction in the instruction stream from being executed due to a branch operation (control hazards) or a data dependency (data hazards). Most computationintensive scientific applications, such as image processing, digital signal processing etc., contain a great number of data hazards and few or no control hazards. In this paper, we present a tool, called SHARP, which was developed to obtain a short schedule while minimizing the underlying data hazards, by exploring loop pipelining and different multiple pipeline architectures. Many computer vendors utilize a forwarding technique to reduce the number of data hazards. This process is implemented on hardware in such a way that a copy of the computed result is sent back to the input prefetch buffer of the processor. However, the larger the number of forwarding buffers, the higher cost will be imposed to the hardware. Therefore, there is a trade-off between its implementation cost and the performance gain. Furthermore, most current modern high speed computer technologies use multiple pipelined functional units (multi-pipelined) or superscalar (super)pipelined architecture, such as MIPS R8000, IBM Power2 RS/6000 and the Intel P6. Computer architects for application-oriented processors can use the tool, proposed in this paper, to determine an appropriate pipeline architecture for a given specific application. By varying the system architecture, such as a number of pipeline units, type of each unit, forwarding buffers etc., one can find a suitable pipeline architecture that balances the hardware and performance costs. 1This work was supported in part by the Royal Thai Government Scholarship, the William D. Mensch, Jr. Fellowship, and by the NSF CAREER grant MIP 95-01006. R W IF ID EX WR Adder Multiplier IF ID R EX WR W